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misc:acronyms [2017/08/07 12:21]
kilov created 		misc:acronyms [2019/01/11 11:11] (current)
edwardw
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 ====== Acronyms and Terms ====== ====== Acronyms and Terms ======
 +
 +=====ADEPT Terms=====
 +
 +  * **ADEPT**:  **A**gile **D**esign of **E**fficient **P**rocessing **T**echnologies
 +  * **BAG**: **B**erkeley **A**nalog **G**enerator: A Chisel like technology for generating analog circuits.
 +  * **BOOM**: **B**erkeley **O**ut-of-**O**rder **M**achine
 +  * **BROOM**: **B**erkeley **R**esilient **O**ut-of-**O**rder **M**achine
 +  * **Chisel Range-analysis**: Instead of declaring a width for a wire instead specify minimum and maximum values.
 +  * **Chisel**: **C**onstructing **H**ardware **i**n a **S**cala **E**mbedded **L**anguage, a generator approach to circuit design.
 +  * **Concolic**: A form of testing that combines the use of **Conc**rete and Symb**olic** values
 +  * **Differentiable Halide**:
 +  * **Diplomacy**: Parameter-negotiation library found in rocket-chip
 +  * **DSSoC**: **D**omain-**s**pecific **S**ystem **o**n **C**hip
 +  * **EAGLE**:
 +  * **F1**: AWS Instance Type with an attached FPGA
 +  * **FCL**: **F**irrtl **C**ommand **L**anguage, a scripting language for firrtl transforms, derived from the Scala REPL (read-eval-print-loop)
 +  * **Firebox**: Novel Computer Architecture for Datacenters
 +  * **FireSim**: **Fire**box **Sim**ulator
 +  * **FIRRTL**: **F**lexible **I**ntermediate **R**epresentation for **RTL**
 +  * **Generator**: A program that generates hardware descriptions
 +  * **Hammer**: Physical design generator.
 +  * **HCL**: **H**ardware **C**onstruction **L**anguage. Generate hardware using better parameterizable hardware abstractions
 +  * **HLS**: **H**igh **L**evel **S**ynthesis, attempts to create hardware from analysis of an generic algorithmic description. In contrast to **HCL**
 +  * **Hwacha**: Generator for RISC-V vector architecture
 +  * **LAMP**: **L**inux-**A**pache-**M**ySQL-**P**HP a software stack that is you need for a complete website. The pieces are now quite fungible.
 +  * **Rocket-Chip**: Generator for RISC-V scalar architecture
 +  * **Shenzhen**:
 +  * **VERGE**:
 +
 +
 +=====General Terms=====
   * **AES**:   Advanced Encryption Standard   * **AES**:   Advanced Encryption Standard
   * **ALU**:   Arithmetic Logic Unit   * **ALU**:   Arithmetic Logic Unit
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   * **WT**:    Write-Through cache   * **WT**:    Write-Through cache
   * **XDR**:   RAMBUS eXtreme Data Rate DRAM   * **XDR**:   RAMBUS eXtreme Data Rate DRAM
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misc/acronyms.1502133718.txt.gz ยท Last modified: 2017/08/07 12:21 by kilov

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