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--- misc:acronyms [2017/11/15 16:07]
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 =====ADEPT Terms=====
-  * **ADEPT**:  Agile hardware Design
+  * **ADEPT**:  **A**gile **D**esign of **E**fficient **P**rocessing **T**echnologies
-  * **Chisel**: Constructing Hardware in a Scala Embedded Language, a generator approach to circuit design.
+  * **BAG**: **B**erkeley **A**nalog **G**enerator: A Chisel like technology for generating analog circuits.
-  * **Generator**: A program that generates hardware descriptions
+  * **BOOM**: **B**erkeley **O**ut-of-**O**rder **M**achine
+  * **BROOM**: **B**erkeley **R**esilient **O**ut-of-**O**rder **M**achine
+  * **Chisel Range-analysis**: Instead of declaring a width for a wire instead specify minimum and maximum values.
+  * **Chisel**: **C**onstructing **H**ardware **i**n a **S**cala **E**mbedded **L**anguage, a generator approach to circuit design.
+  * **Concolic**: A form of testing that combines the use of **Conc**rete and Symb**olic** values
   * **Differentiable Halide**:
-  * **Hwacha**: Generator for RISC-V vector architecture
+  * **Diplomacy**: Parameter-negotiation library found in rocket-chip
-  * **FireSim**: Firebox Simulator
+  * **DSSoC**: **D**omain-**s**pecific **S**ystem **o**n **C**hip
+  * **EAGLE**:
+  * **F1**: AWS Instance Type with an attached FPGA
+  * **FCL**: **F**irrtl **C**ommand **L**anguage, a scripting language for firrtl transforms, derived from the Scala REPL (read-eval-print-loop)
   * **Firebox**: Novel Computer Architecture for Datacenters
-  * **Chisel Range-analysis**: Instead of declaring a width for a wire instead specify minimum and maximum values.
+  * **FireSim**: **Fire**box **Sim**ulator
-  * **Hammer**:
+  * **FIRRTL**: **F**lexible **I**ntermediate **R**epresentation for **RTL**
-  * **FCL**: Firrtl Command Loop, a scripting language for firrtl transforms, derived from the Scala REPL (read-eval-print-loop)
+  * **Generator**: A program that generates hardware descriptions
-  * **F1**:
+  * **Hammer**: Physical design generator.
-  * **BOOM**: Berkeley Out-of-Order Machine
+  * **HCL**: **H**ardware **C**onstruction **L**anguage. Generate hardware using better parameterizable hardware abstractions
-  * **BROOM**: Berkeley Resilient Out-of-Order Machine
+  * **HLS**: **H**igh **L**evel **S**ynthesis, attempts to create hardware from analysis of an generic algorithmic description. In contrast to **HCL**
-  * **Concolic**: A form of testing that combines the use of *Conc*rete and Symb*olic* values
+  * **Hwacha**: Generator for RISC-V vector architecture
-  * **VERGE**:
+  * **LAMP**: **L**inux-**A**pache-**M**ySQL-**P**HP a software stack that is you need for a complete website. The pieces are now quite fungible.
-  * **DSSoC**: Domain-specific System on Chip
-  * **BAG**: Berkeley Analog Generator: A Chisel like technology for generating analog circuits.
-  * **Diplomacy**:
   * **Rocket-Chip**: Generator for RISC-V scalar architecture
-  * **HLS**:
-  * **EAGLE**:
-  * **FIRRTL**: Flexible Intermediate Representation for RTL
-  * **LAMP**: Linux-Apache-MySQL-PHP a software stack that is you need for a complete website. The pieces are now quite fungible.
   * **Shenzhen**:
+  * **VERGE**:
 =====General Terms=====

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