Adept Lab at UCBerkeley

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Introduction

The end of historic CMOS transistor scaling and the lack of feasible technology alternatives would appear to place a major roadblock on the path to future innovations in computing capability. But the demise of Moore’s Law’s is largely irrelevant for most of the hardware industry, because manufacturing is not the problem.  CMOS, at the end of scaling, is an almost magical technology.  The real problem is that upfront NRE (non-recurring engineering) design costs dominate marginal manufacturing cost per transistor for all except a few high-volume products, but a few mass-produced standard products are a poor fit for all the new applications demanding cost-effective energy-efficient computing in a wide range of form factors, from warehouse-scale computers to tiny sensor nodes.  The real roadblock to innovation i not the performance of an individual transistor or the cost of manufacturing, but that fewer and fewer projects can afford the custom silicon needed to best exploit existing CMOS manufacturing technology.  Industry must transition from its current fixation on Moore’s Law, to a new goal of reducing NRE/transistor by a factor of two every 12 months.    The ADEPT (Agile Design of Efficient Processing Technologies) Lab is a new 5-year project that builds on our earlier work on the free and open RISC-V ISA and the open-source Chisel hardware design language to address all components of upfront design cost and thereby help democratize access to custom silicon.  We are using two different application areas, warehouse-scale computing (WSC), and high-performance embedded computing, to drive our research.

Software

Software is a large component of new chip design costs, and we are exploring new high-level programming models, including serverless models for the cloud, and specialized DSLs, such as Halide, for embedded computing.  These high-level programming systems simplify the introduction of specialized hardware by separating high-level specification of application function from low-level details of application mapping onto a hardware substrate.  At the system software level, we are leveraging the flexibility of the RISC-V ISA to enable a wide range of domain-specialized accelerators to nevertheless share similar programming tools.

Architecture

We are exploring new customizable architecture models, including extensions to the RISC-V vector extensions to support instructions that operate on application-specific “shapes” beyond simple 1D vectors in the Eagle project.  For the datacenter, we are exploring the creation of custom accelerator SoCs that connect directly to a high-radix photonic network backplane (IceNet) and pooled bulk memory in the FireBox project.

Hardware Design and Verification

Continuing and expanding our work on productive hardware design methodologies, we are expanding the Chisel language to provide better support for formal and dynamic verification methodologies, and expanding our work on the FIRRTL intermediate representation to support physical design and other parts of the full chip design flow.  In the MIDAS project, we build upon techniques developed in our earlier RAMP project to automatically create high-performance FPGA-accelerated simulation models, with the largest incarnation being FireSim, which can faithfully model thousands of servers in a datacenter cluster at the RTL level.