Fully Automated Analog Sub-Circuit Clustering with Graph Convolutional Neural Networks

The design of custom analog integrated circuits isa contributing factor in high development cost and increased production time, driving the need for more automation. In automating particular avenues of analog design, it is then crucial to assess the efficacy with which the algorithm is able to solve the desired problem. To do this, one must consider four metrics that are especially pertinent in this area: robustness, accuracy, level of automation, and computation time. In this work, we present a framework that bridges the gap between schematic and layout generation by encapsulating the design intuition needed to create layout through identification of critical sub-circuit structures through the use of Graphical Convolutional Neural Networks(GCNNs) along with an unsupervised graph clustering technique. This framework is the first tool, to our knowledge, to entirely automate this clustering process. We compare our algorithm to prior work utilizing the four figures of merit, and our results show over 90% accuracy across six different analog circuits, ranging in size and complexity, while taking just under 1 second to complete.