The Hydra Spine ASIC is part of a massive MIMO system demonstrator at Berkeley. The ASIC (as of Summer 2020) is the latest chip to be taped out at Berkeley using the Chipyard framework. The mixed-signal chip was taped out at the end of April 2020 in the Intel 22FFL process, and is comprised of 8 uplink + downlink channels performing baseband digital signal processing. ADCs, DACs, and other analog IP were generated using BAG; the channel estimation, timing correction, and signal correction DSP were generated with Chisel; and physical design was accelerated with HAMMER. The Chisel generator is also concurrently undergoing emulation on an FPGA platform. We intend to show that it is possible for small teams to build custom accelerators for scalable massive MIMO systems using agile design and generator frameworks, and we look forward to testing the chip later this year.