Papers CoSA: Scheduling by Constrained Optimization for Spatial Accelerators May 19, 2021 Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration May 18, 2021 FireMarshal: Making HW/SW Co-Design Reproducible and Reliable May 17, 2021 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET April 2, 2021 Programmable Fine-Grained Power Management and System Analysis of RISC-V Vector Processors in 28-nm FD-SOI July 22, 2020 Chipyard - An Integrated SoC Research and Implementation Environment July 5, 2020 Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs July 5, 2020 Keystone: an Open Framework for Architecting Trusted Execution Environments April 28, 2020 An Off-Chip Attack on Hardware Enclaves via the Memory Bus April 27, 2020 RLDRM: Closed Loop Dynamic Cache Allocation with Deep Reinforcement Learning for Network Function Virtualization April 27, 2020 NeuroVectorizer: End-to-End Vectorization with Deep Reinforcement Learning April 27, 2020 AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning April 27, 2020 Fully Automated Analog Sub-Circuit Clustering with Graph Convolutional Neural Networks April 27, 2020 AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs April 27, 2020 FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design December 23, 2019 Co-Design of Deep Neural Nets and Neural Net Accelerators for Embedded Vision Applications November 5, 2019 The Serverless Data Center: Hardware Disaggregation Meets Serverless Computing September 3, 2019 Exploring the Disaggregated Memory Interface Design Space September 3, 2019 Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes August 22, 2019 FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud (IEEE Micro Top Picks 2018) April 11, 2019 FASED: FPGA-Accelerated Simulation and Evaluation of DRAM March 6, 2019 Opt: A Domain Specific Language for Non-linear Least Squares Optimization in Graphics and Imaging March 5, 2019 Differentiable Programming for Image Processing and Deep Learning in Halide March 5, 2019 FPGA Accelerated INDEL Realignment in the Cloud March 5, 2019 Hammer: Enabling Reusable Physical Design March 5, 2019 DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of cycles July 21, 2018 RFUZZ: Coverage-Directed Fuzz Testing of RTL on FPGAs July 17, 2018 A Hardware Accelerator for Tracing Garbage Collection June 26, 2018 FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud June 5, 2018
CoSA: Scheduling by Constrained Optimization for Spatial Accelerators May 19, 2021 Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration May 18, 2021 FireMarshal: Making HW/SW Co-Design Reproducible and Reliable May 17, 2021 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET April 2, 2021 Programmable Fine-Grained Power Management and System Analysis of RISC-V Vector Processors in 28-nm FD-SOI July 22, 2020 Chipyard - An Integrated SoC Research and Implementation Environment July 5, 2020 Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs July 5, 2020 Keystone: an Open Framework for Architecting Trusted Execution Environments April 28, 2020 An Off-Chip Attack on Hardware Enclaves via the Memory Bus April 27, 2020 RLDRM: Closed Loop Dynamic Cache Allocation with Deep Reinforcement Learning for Network Function Virtualization April 27, 2020 NeuroVectorizer: End-to-End Vectorization with Deep Reinforcement Learning April 27, 2020 AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning April 27, 2020 Fully Automated Analog Sub-Circuit Clustering with Graph Convolutional Neural Networks April 27, 2020 AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs April 27, 2020 FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design December 23, 2019 Co-Design of Deep Neural Nets and Neural Net Accelerators for Embedded Vision Applications November 5, 2019 The Serverless Data Center: Hardware Disaggregation Meets Serverless Computing September 3, 2019 Exploring the Disaggregated Memory Interface Design Space September 3, 2019 Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes August 22, 2019 FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud (IEEE Micro Top Picks 2018) April 11, 2019 FASED: FPGA-Accelerated Simulation and Evaluation of DRAM March 6, 2019 Opt: A Domain Specific Language for Non-linear Least Squares Optimization in Graphics and Imaging March 5, 2019 Differentiable Programming for Image Processing and Deep Learning in Halide March 5, 2019 FPGA Accelerated INDEL Realignment in the Cloud March 5, 2019 Hammer: Enabling Reusable Physical Design March 5, 2019 DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of cycles July 21, 2018 RFUZZ: Coverage-Directed Fuzz Testing of RTL on FPGAs July 17, 2018 A Hardware Accelerator for Tracing Garbage Collection June 26, 2018 FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud June 5, 2018
